Peripheral Component Interconnect (PCI) configuration space is utilized by systems employing PCI, PCI-X, and PCI Express (PCIe) to perform configuration tasks of PCI-based devices. PCI-based devices have an address space for device configuration registers referred to as configuration space, and PCI Express introduces extended configuration space for devices. Configuration space registers are typically mapped to memory mapped input/output locations by the host processor. Device drivers, operating systems, and diagnostic software access the configuration space and can read and write information to configuration space registers.
One of the improvements the PCI Local Bus had over other I/O architectures was its configuration mechanism. In addition to the normal memory-mapped and I/O port spaces, each device function on the bus has a configuration space, which is 256 bytes long, addressable by knowing the eight-bit PCI bus, five-bit device, and three-bit function numbers for the device (commonly referred to as the BDF or B/D/F, as abbreviated from bus/device/function). This allows up to 256 buses, each with up to 32 devices, each supporting eight functions. A single PCI expansion card can respond as a device and can implement at least a function number zero. The first 64 bytes of configuration space are standardized; the remainder are available specification defined extensions and/or for vendor-defined purposes.
In order to allow more parts of configuration space to be standardized without conflicting with existing uses, there can be a list of capabilities defined within the first 192 bytes of Peripheral Component Interface configuration space. Each capability has one byte that describes which capability it is, and one byte to point to the next capability. The number of additional bytes depends on the capability ID. If capabilities are being used, a bit in the Status register is set, and a pointer to the first in a linked list of capabilities is provided. Previous versions of PCIe have been provided with similar features, such as a PCIe extended capabilities structure.